1. Field of the Invention
It is related to communication test circuits, communication interface circuits, and communication test methods, and particularly to a communication test circuit for testing a communication interface circuit which restores a clock signal and detects data, from a received signal, the communication interface circuit, and a communication test method thereof.
2. Description of the Related Art
Since the performance of elements such as components included in computers and other information processing apparatuses has been enhanced in recent years, a high-speed serial interface that increases the data transfer speed between elements has become an item that must be incorporated.
A receiving circuit of the high-speed serial interface must detect data at a correct timing with respect to a sent signal. Therefore, the receiving circuit has a clock data recovery (CDR) circuit for carrying out a phase adjustment so that a correct clock can be generated from the received signal.
FIG. 5 is a block diagram showing an example structure of a conventional CDR circuit.
The conventional CDR circuit includes a data latch block 901, a boundary latch block 902, a boundary clock generation block 903, a data latch clock generation block 904, and a phase adjustment code generation block 905. The data latch block 901 operates according to a data latch clock signal generated by the data latch clock generation block 904 and latches data from an input differential signal. The boundary latch block 902 operates according to a boundary clock signal generated by the boundary clock generation block 903 and latches the boundary of the same input signal. The phase adjustment code generation block 905 compares the latch timing of the boundary latch block 902 and a data transition timing of the input signal to determine a phase lead or a phase lag, generates a phase adjustment code for bringing the boundary clock signal in phase with the actual input signal, and outputs the code to the boundary clock generation block 903. The phase of the boundary clock signal is adjusted accordingly. In addition, the data latch clock signal is adjusted to align its edge always with the midpoint between two edges of the boundary clock signal. One proposed clock restoration circuit (refer to Japanese Unexamined Patent Application Publication No. 2002-314516, FIG. 4, for instance) performs a stable clock restoration operation by shifting a boundary detection timing in advance or afterwards from the natural timing on purpose to change the boundary detection timing.
Standards for the receiving circuit of the serial interface define the maximum allowable jitter (noise measured in time). The receiving circuit must be able to receive a signal containing noise in the time domain up to the maximum allowable jitter. Therefore, the receiving circuit is factory-tested on jitter tolerance to check whether it can detect correct data from the received signal containing the maximum allowable jitter.
In the jitter tolerance test, the receiving circuit is given actual data bearing predetermined jitter. This can be implemented in some ways: A tester may generate an input signal carrying jitter and input the signal to the receiving circuit; an external component mounted on a test board may introduce jitter to an input signal. The test may be performed such that a jitter test circuit provided in the serial interface circuit (including input and output) introduces jitter to transmission data by giving jitter to a clock signal supplied to a sending circuit, and the transmission data is input to the receiving circuit (refer to Japanese Unexamined Patent Application Publication No. 2005-4653, FIG. 1, for instance).
A conventional jitter tolerance testing method is inappropriate for the high-speed serial interface that sends and receives high-speed serial data.
Generally, the signal transmission rate of the high-speed serial interface exceeds 1 Gbps and is expected to be higher in the future. For example, Peripheral Component Interconnect (PCI) Express performs 2.5-Gbps high-speed differential pulse transmission through a two-wire lane in one direction.
In a basic testing environment, high-speed serial data carrying jitter are generated, and the high-speed serial data is input to the receiving circuit for the test. A general LSI tester, however, does not have a function to generate jitter. If a tester is used, a tester that can measure jitter tolerance must be used. The tester that can measure jitter tolerance is so expensive that it would be hard to prepare a plurality of testers. It would be unfeasible to use those testers in a test in mass production. If the data transmission rate is high, a high precision would be required.
If jitter is introduced by an external component mounted on a test board, much effort would be needed to build the testing environment because the test board must be made in addition to the product. In addition, the test board would need complicated maintenance, and it would be hard to ensure the precision of the test board.
If jitter is introduced to the clock signal supplied to the sending circuit to input a signal bearing jitter into the receiving circuit, a test circuit for generating and adding jitter to the transmission data must be designed in addition to the product, requiring effort.
In view of the foregoing, it is an object of the present invention to provide a communication test circuit, a communication interface circuit, and a communication test method that allow a tolerance test such as a jitter tolerance test for mass-produced products to be carried out in a general environment.